1. Field of the Invention
The present invention generally relates to technology of forming interlayer dielectric films for multilayer interconnection for semiconductor integrated circuits, particularly to a method for forming a gap-fill carbon-doped silicon oxide (SiOCH) film on a patterned surface of a substrate where recessed features between wiring lines are narrow.
2. Description of the Related Art
In recent years, the development of semiconductor devices has been remarkable, and has achieved high integration, high speed, and high capacity, and accordingly, the miniaturization of interconnection of semiconductor circuits has progressed. As the miniaturization of interconnection progresses, signal delay and increase in power consumption associated with increase of wiring capacitance especially in a multilayer wiring structure have become a problem. To solve the problem, an insulation film with a low dielectric constant, which is a SiOCH film, is used as a multilayer interconnection dielectric film so as to reduce capacitance between wiring lines. Further, copper is used as a wiring material for reducing resistivity to improve signal delay. The typical method for forming multilayer interconnection using the SiOCH film and copper is the damascene method.
The damascene method is accomplished by firstly depositing a SiOCH film, and then forming a trench or a via hole in the SiOCH film by an exposure/etching process, and then embedding copper in the trench or the via hole. The damascene method has been the main technology of low-k film multilayer interconnection for a long time. However, as the miniaturization of interconnection has further progressed, the resistance of copper as the wiring material rises according to the width of the interconnection, and therefore the advantage of using copper has diminished. By its nature, copper easily defuses in the SiOCH film, and therefore when copper is used as the wiring material, a complicated process to prevent copper from diffusing in the SiOCH film is required. Therefore, tungsten, which has traditionally been used as a wiring material, draws attention as a new wiring material in multilayer connection structures. If tungsten is used as the wiring material, the complicated process is not required, and process cost is reduced by a simplified process.
When tungsten is used as the wiring material, the damascene method is not necessary due to the fact that tungsten is easy to etch as compared with copper, and a conventional method of first forming metal wiring and then forming interlayer interconnection dielectric film between metal wiring lines can be used. In this case, since extremely narrow intervals are formed between metal wiring lines, the intervals are not filled completely by the conventional CVD method, and accordingly voids and the like are formed in the interlayer dielectric film. In order to solve the problem of void formation, a flowable CVD method, ALD method, and spin-coat method have been developed. After a SiOCH film is formed by those methods, UV-curing process is conducted on the SiOCH film so as to lower the dielectric constant and stabilize the SiOCH film.
However, after tungsten wiring is complete, followed by filling intervals between the wiring lines with a SiOCH film by flowable CVD, ALD, or spin coating, when UV-curing is conducted for lowering dielectric constant and stabilization of the film, film shrinkage occurs. If film shrinkage is significant, disconnection of wiring lines and collapse of wiring lines occur due to shrinking force. Further, cracks of the film itself may occur.
Conventionally, the above problem is solved by “annealing” the film for stabilizing the film to a certain degree at a relatively low temperature such as 50° C. to 100° C. or at a temperature increasing gradually or stepwise, prior to high-temperature UV-curing. However, once the film is heated, film shrinkage during high-temperature UV-curing remains high and is not significantly improved.
Any discussion of problems and solutions involved in the related art has been included in this disclosure solely for the purposes of providing a context for the present invention, and should not be taken as an admission that any or all of the discussion were known at the time the invention was made.